RadioHead
radio_config_Si4460.h
1 /*! @file radio_config.h
2  * @brief This file contains the automatically generated
3  * configurations.
4  *
5  * @n WDS GUI Version: 3.2.11.0
6  * @n Device: Si4460 Rev.: C2
7  *
8  * @b COPYRIGHT
9  * @n Silicon Laboratories Confidential
10  * @n Copyright 2017 Silicon Laboratories, Inc.
11  * @n http://www.silabs.com
12  */
13 
14 #ifndef RADIO_CONFIG_H_
15 #define RADIO_CONFIG_H_
16 
17 // USER DEFINED PARAMETERS
18 // Define your own parameters here
19 
20 // INPUT DATA
21 /*
22 // Crys_freq(Hz): 30000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
23 // MOD_type: 3 Rsymb(sps): 10000 Fdev(Hz): 20000 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2
24 // RF Freq.(MHz): 434 API_TC: 29 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1
25 // API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 0
26 //
27 // # RX IF frequency is -468750 Hz
28 // # WB filter 4 (BW = 82.64 kHz); NB-filter 4 (BW = 82.64 kHz)
29 //
30 // Modulation index: 4
31 */
32 
33 
34 // CONFIGURATION PARAMETERS
35 #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 30000000L
36 #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00
37 #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x07
38 #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03
39 #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000
40 
41 #include "..\drivers\radio\Si446x\si446x_patch.h"
42 
43 
44 // CONFIGURATION COMMANDS
45 
46 /*
47 // Command: RF_POWER_UP
48 // Description: Command to power-up the device and select the operational mode and functionality.
49 */
50 #define RF_POWER_UP 0x02, 0x81, 0x00, 0x01, 0xC9, 0xC3, 0x80
51 
52 /*
53 // Command: RF_GPIO_PIN_CFG
54 // Description: Configures the GPIO pins.
55 */
56 #define RF_GPIO_PIN_CFG 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
57 
58 /*
59 // Set properties: RF_GLOBAL_XO_TUNE_2
60 // Number of properties: 2
61 // Group ID: 0x00
62 // Start ID: 0x00
63 // Default values: 0x40, 0x00,
64 // Descriptions:
65 // GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
66 // GLOBAL_CLK_CFG - Clock configuration options.
67 */
68 #define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x52, 0x00
69 
70 /*
71 // Set properties: RF_GLOBAL_CONFIG_1
72 // Number of properties: 1
73 // Group ID: 0x00
74 // Start ID: 0x03
75 // Default values: 0x20,
76 // Descriptions:
77 // GLOBAL_CONFIG - Global configuration settings.
78 */
79 #define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
80 
81 /*
82 // Set properties: RF_INT_CTL_ENABLE_1
83 // Number of properties: 1
84 // Group ID: 0x01
85 // Start ID: 0x00
86 // Default values: 0x04,
87 // Descriptions:
88 // INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
89 */
90 #define RF_INT_CTL_ENABLE_1 0x11, 0x01, 0x01, 0x00, 0x00
91 
92 /*
93 // Set properties: RF_FRR_CTL_A_MODE_4
94 // Number of properties: 4
95 // Group ID: 0x02
96 // Start ID: 0x00
97 // Default values: 0x01, 0x02, 0x09, 0x00,
98 // Descriptions:
99 // FRR_CTL_A_MODE - Fast Response Register A Configuration.
100 // FRR_CTL_B_MODE - Fast Response Register B Configuration.
101 // FRR_CTL_C_MODE - Fast Response Register C Configuration.
102 // FRR_CTL_D_MODE - Fast Response Register D Configuration.
103 */
104 #define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00
105 
106 /*
107 // Set properties: RF_PREAMBLE_TX_LENGTH_9
108 // Number of properties: 9
109 // Group ID: 0x10
110 // Start ID: 0x00
111 // Default values: 0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00,
112 // Descriptions:
113 // PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
114 // PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
115 // PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
116 // PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
117 // PREAMBLE_CONFIG - General configuration bits for the Preamble field.
118 // PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
119 // PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
120 // PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
121 // PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
122 */
123 #define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x08, 0x14, 0x00, 0x0F, 0x31, 0x00, 0x00, 0x00, 0x00
124 
125 /*
126 // Set properties: RF_SYNC_CONFIG_6
127 // Number of properties: 6
128 // Group ID: 0x11
129 // Start ID: 0x00
130 // Default values: 0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00,
131 // Descriptions:
132 // SYNC_CONFIG - Sync Word configuration bits.
133 // SYNC_BITS_31_24 - Sync word.
134 // SYNC_BITS_23_16 - Sync word.
135 // SYNC_BITS_15_8 - Sync word.
136 // SYNC_BITS_7_0 - Sync word.
137 // SYNC_CONFIG2 - Sync Word configuration bits.
138 */
139 #define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x01, 0xB4, 0x2B, 0x00, 0x00, 0x00
140 
141 /*
142 // Set properties: RF_PKT_CRC_CONFIG_12
143 // Number of properties: 12
144 // Group ID: 0x12
145 // Start ID: 0x00
146 // Default values: 0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
147 // Descriptions:
148 // PKT_CRC_CONFIG - Select a CRC polynomial and seed.
149 // PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
150 // PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
151 // PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
152 // PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
153 // PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
154 // PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
155 // PKT_CONFIG2 - General packet configuration bits.
156 // PKT_LEN - Configuration bits for reception of a variable length packet.
157 // PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
158 // PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
159 // PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
160 */
161 #define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x00, 0x30, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x00, 0x00, 0x00, 0x30
162 
163 /*
164 // Set properties: RF_PKT_RX_THRESHOLD_12
165 // Number of properties: 12
166 // Group ID: 0x12
167 // Start ID: 0x0C
168 // Default values: 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
169 // Descriptions:
170 // PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
171 // PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
172 // PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
173 // PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
174 // PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
175 // PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
176 // PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
177 // PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
178 // PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
179 // PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
180 // PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
181 // PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
182 */
183 #define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x30, 0x00, 0x07, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
184 
185 /*
186 // Set properties: RF_PKT_FIELD_3_CRC_CONFIG_12
187 // Number of properties: 12
188 // Group ID: 0x12
189 // Start ID: 0x18
190 // Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
191 // Descriptions:
192 // PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
193 // PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
194 // PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
195 // PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
196 // PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
197 // PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
198 // PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
199 // PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
200 // PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
201 // PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
202 // PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
203 // PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
204 */
205 #define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
206 
207 /*
208 // Set properties: RF_PKT_RX_FIELD_1_CRC_CONFIG_12
209 // Number of properties: 12
210 // Group ID: 0x12
211 // Start ID: 0x24
212 // Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
213 // Descriptions:
214 // PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
215 // PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
216 // PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
217 // PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
218 // PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
219 // PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
220 // PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
221 // PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
222 // PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
223 // PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
224 // PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
225 // PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
226 */
227 #define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
228 
229 /*
230 // Set properties: RF_PKT_RX_FIELD_4_CRC_CONFIG_5
231 // Number of properties: 5
232 // Group ID: 0x12
233 // Start ID: 0x30
234 // Default values: 0x00, 0x00, 0x00, 0x00, 0x00,
235 // Descriptions:
236 // PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
237 // PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
238 // PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
239 // PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
240 // PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
241 */
242 #define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
243 
244 /*
245 // Set properties: RF_PKT_CRC_SEED_31_24_4
246 // Number of properties: 4
247 // Group ID: 0x12
248 // Start ID: 0x36
249 // Default values: 0x00, 0x00, 0x00, 0x00,
250 // Descriptions:
251 // PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
252 // PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
253 // PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
254 // PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
255 */
256 #define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
257 
258 /*
259 // Set properties: RF_MODEM_MOD_TYPE_12
260 // Number of properties: 12
261 // Group ID: 0x20
262 // Start ID: 0x00
263 // Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
264 // Descriptions:
265 // MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
266 // MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
267 // MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
268 // MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
269 // MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
270 // MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
271 // MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
272 // MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
273 // MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
274 // MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
275 // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
276 // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
277 */
278 #define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x06, 0x1A, 0x80, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x05
279 
280 /*
281 // Set properties: RF_MODEM_FREQ_DEV_0_1
282 // Number of properties: 1
283 // Group ID: 0x20
284 // Start ID: 0x0C
285 // Default values: 0xD3,
286 // Descriptions:
287 // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
288 */
289 #define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x76
290 
291 /*
292 // Set properties: RF_MODEM_TX_RAMP_DELAY_12
293 // Number of properties: 12
294 // Group ID: 0x20
295 // Start ID: 0x18
296 // Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B,
297 // Descriptions:
298 // MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
299 // MODEM_MDM_CTRL - MDM control.
300 // MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
301 // MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
302 // MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
303 // MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
304 // MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
305 // MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
306 // MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
307 // MODEM_IFPKD_THRESHOLDS -
308 // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
309 // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
310 */
311 #define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x20, 0x20, 0x00, 0xE8, 0x01, 0x77
312 
313 /*
314 // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12
315 // Number of properties: 12
316 // Group ID: 0x20
317 // Start ID: 0x24
318 // Default values: 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69,
319 // Descriptions:
320 // MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
321 // MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
322 // MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
323 // MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
324 // MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
325 // MODEM_BCR_GEAR - RX BCR loop gear control.
326 // MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
327 // MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
328 // MODEM_AFC_GEAR - RX AFC loop gear control.
329 // MODEM_AFC_WAIT - RX AFC loop wait time control.
330 // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
331 // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
332 */
333 #define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x01, 0x5D, 0x86, 0x00, 0xAF, 0x02, 0xC2, 0x00, 0x04, 0x23, 0x80, 0x1D
334 
335 /*
336 // Set properties: RF_MODEM_AFC_LIMITER_1_3
337 // Number of properties: 3
338 // Group ID: 0x20
339 // Start ID: 0x30
340 // Default values: 0x00, 0x40, 0xA0,
341 // Descriptions:
342 // MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
343 // MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
344 // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
345 */
346 #define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x10, 0x04, 0x80
347 
348 /*
349 // Set properties: RF_MODEM_AGC_CONTROL_1
350 // Number of properties: 1
351 // Group ID: 0x20
352 // Start ID: 0x35
353 // Default values: 0xE0,
354 // Descriptions:
355 // MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
356 */
357 #define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
358 
359 /*
360 // Set properties: RF_MODEM_AGC_WINDOW_SIZE_12
361 // Number of properties: 12
362 // Group ID: 0x20
363 // Start ID: 0x38
364 // Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03,
365 // Descriptions:
366 // MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
367 // MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
368 // MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
369 // MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
370 // MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
371 // MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
372 // MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
373 // MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
374 // MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
375 // MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
376 // MODEM_OOK_CNT1 - OOK control.
377 // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
378 */
379 #define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x52, 0x52, 0x80, 0x1A, 0xFF, 0xFF, 0x00, 0x2A, 0x0C, 0xA4, 0x22
380 
381 /*
382 // Set properties: RF_MODEM_RAW_CONTROL_10
383 // Number of properties: 10
384 // Group ID: 0x20
385 // Start ID: 0x45
386 // Default values: 0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40,
387 // Descriptions:
388 // MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
389 // MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
390 // MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
391 // MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
392 // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
393 // MODEM_RSSI_THRESH - Configures the RSSI threshold.
394 // MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
395 // MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
396 // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
397 // MODEM_RSSI_COMP - RSSI compensation value.
398 */
399 #define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x83, 0x00, 0xDE, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x18, 0x40
400 
401 /*
402 // Set properties: RF_MODEM_RAW_SEARCH2_2
403 // Number of properties: 2
404 // Group ID: 0x20
405 // Start ID: 0x50
406 // Default values: 0x00, 0x08,
407 // Descriptions:
408 // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
409 // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
410 */
411 #define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x84, 0x0A
412 
413 /*
414 // Set properties: RF_MODEM_SPIKE_DET_2
415 // Number of properties: 2
416 // Group ID: 0x20
417 // Start ID: 0x54
418 // Default values: 0x00, 0x00,
419 // Descriptions:
420 // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
421 // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
422 */
423 #define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
424 
425 /*
426 // Set properties: RF_MODEM_RSSI_MUTE_1
427 // Number of properties: 1
428 // Group ID: 0x20
429 // Start ID: 0x57
430 // Default values: 0x00,
431 // Descriptions:
432 // MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
433 */
434 #define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
435 
436 /*
437 // Set properties: RF_MODEM_DSA_CTRL1_5
438 // Number of properties: 5
439 // Group ID: 0x20
440 // Start ID: 0x5B
441 // Default values: 0x00, 0x00, 0x00, 0x00, 0x00,
442 // Descriptions:
443 // MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
444 // MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
445 // MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
446 // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
447 // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
448 */
449 #define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x07, 0x78, 0x20
450 
451 /*
452 // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
453 // Number of properties: 12
454 // Group ID: 0x21
455 // Start ID: 0x00
456 // Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01,
457 // Descriptions:
458 // MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
459 // MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
460 // MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
461 // MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
462 // MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
463 // MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
464 // MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
465 // MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
466 // MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
467 // MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
468 // MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
469 // MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
470 */
471 #define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08
472 
473 /*
474 // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
475 // Number of properties: 12
476 // Group ID: 0x21
477 // Start ID: 0x0C
478 // Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5,
479 // Descriptions:
480 // MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
481 // MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
482 // MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
483 // MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
484 // MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
485 // MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
486 // MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
487 // MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
488 // MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
489 // MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
490 // MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
491 // MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
492 */
493 #define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE
494 
495 /*
496 // Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
497 // Number of properties: 12
498 // Group ID: 0x21
499 // Start ID: 0x18
500 // Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
501 // Descriptions:
502 // MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
503 // MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
504 // MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
505 // MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
506 // MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
507 // MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
508 // MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
509 // MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
510 // MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
511 // MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
512 // MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
513 // MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
514 */
515 #define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00
516 
517 /*
518 // Set properties: RF_PA_MODE_4
519 // Number of properties: 4
520 // Group ID: 0x22
521 // Start ID: 0x00
522 // Default values: 0x08, 0x7F, 0x00, 0x5D,
523 // Descriptions:
524 // PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
525 // PA_PWR_LVL - Configuration of PA output power level.
526 // PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
527 // PA_TC - Configuration of PA ramping parameters.
528 */
529 #define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x18, 0x2C, 0xC0, 0x1D
530 
531 /*
532 // Set properties: RF_SYNTH_PFDCP_CPFF_7
533 // Number of properties: 7
534 // Group ID: 0x23
535 // Start ID: 0x00
536 // Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
537 // Descriptions:
538 // SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
539 // SYNTH_PFDCP_CPINT - Integration charge pump current selection.
540 // SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
541 // SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
542 // SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
543 // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
544 // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
545 */
546 #define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
547 
548 /*
549 // Set properties: RF_MATCH_VALUE_1_12
550 // Number of properties: 12
551 // Group ID: 0x30
552 // Start ID: 0x00
553 // Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
554 // Descriptions:
555 // MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
556 // MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
557 // MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
558 // MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
559 // MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
560 // MATCH_CTRL_2 - Configuration of Match Byte 2.
561 // MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
562 // MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
563 // MATCH_CTRL_3 - Configuration of Match Byte 3.
564 // MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
565 // MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
566 // MATCH_CTRL_4 - Configuration of Match Byte 4.
567 */
568 #define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
569 
570 /*
571 // Set properties: RF_FREQ_CONTROL_INTE_8
572 // Number of properties: 8
573 // Group ID: 0x40
574 // Start ID: 0x00
575 // Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
576 // Descriptions:
577 // FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
578 // FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
579 // FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
580 // FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
581 // FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
582 // FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
583 // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
584 // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
585 */
586 #define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x38, 0x0E, 0xEE, 0xEE, 0x44, 0x44, 0x20, 0xFE
587 
588 
589 // AUTOMATICALLY GENERATED CODE!
590 // DO NOT EDIT/MODIFY BELOW THIS LINE!
591 // --------------------------------------------
592 
593 #ifndef FIRMWARE_LOAD_COMPILE
594 #define RADIO_CONFIGURATION_DATA_ARRAY { \
595  SI446X_PATCH_CMDS, \
596  0x07, RF_POWER_UP, \
597  0x08, RF_GPIO_PIN_CFG, \
598  0x06, RF_GLOBAL_XO_TUNE_2, \
599  0x05, RF_GLOBAL_CONFIG_1, \
600  0x05, RF_INT_CTL_ENABLE_1, \
601  0x08, RF_FRR_CTL_A_MODE_4, \
602  0x0D, RF_PREAMBLE_TX_LENGTH_9, \
603  0x0A, RF_SYNC_CONFIG_6, \
604  0x10, RF_PKT_CRC_CONFIG_12, \
605  0x10, RF_PKT_RX_THRESHOLD_12, \
606  0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
607  0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
608  0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
609  0x08, RF_PKT_CRC_SEED_31_24_4, \
610  0x10, RF_MODEM_MOD_TYPE_12, \
611  0x05, RF_MODEM_FREQ_DEV_0_1, \
612  0x10, RF_MODEM_TX_RAMP_DELAY_12, \
613  0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
614  0x07, RF_MODEM_AFC_LIMITER_1_3, \
615  0x05, RF_MODEM_AGC_CONTROL_1, \
616  0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
617  0x0E, RF_MODEM_RAW_CONTROL_10, \
618  0x06, RF_MODEM_RAW_SEARCH2_2, \
619  0x06, RF_MODEM_SPIKE_DET_2, \
620  0x05, RF_MODEM_RSSI_MUTE_1, \
621  0x09, RF_MODEM_DSA_CTRL1_5, \
622  0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
623  0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
624  0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
625  0x08, RF_PA_MODE_4, \
626  0x0B, RF_SYNTH_PFDCP_CPFF_7, \
627  0x10, RF_MATCH_VALUE_1_12, \
628  0x0C, RF_FREQ_CONTROL_INTE_8, \
629  0x00 \
630  }
631 #else
632 #define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
633 #endif
634 
635 // DEFAULT VALUES FOR CONFIGURATION PARAMETERS
636 #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L
637 #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00
638 #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10
639 #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01
640 #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000
641 
642 #define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00
643 #define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00
644 #define RADIO_CONFIGURATION_DATA_RADIO_PATCH { }
645 
646 #ifndef RADIO_CONFIGURATION_DATA_ARRAY
647 #error "This property must be defined!"
648 #endif
649 
650 #ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
651 #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT
652 #endif
653 
654 #ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
655 #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT
656 #endif
657 
658 #ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
659 #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT
660 #endif
661 
662 #ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
663 #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT
664 #endif
665 
666 #ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
667 #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT
668 #endif
669 
670 #define RADIO_CONFIGURATION_DATA { \
671  Radio_Configuration_Data_Array, \
672  RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \
673  RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \
674  RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \
675  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \
676  }
677 
678 #endif /* RADIO_CONFIG_H_ */
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