Macros
#define	HIGH 0x1
	This means pin HIGH, true, 3.3volts on a pin.
#define	LOW 0x0
	This means pin LOW, false, 0volts on a pin.
#define	BCM2835_CORE_CLK_HZ 250000000
	Speed of the core clock core_clk.
#define	BCM2835_PERI_BASE 0x20000000
	Base Physical Address of the BCM 2835 peripheral registers.
#define	BCM2835_ST_BASE (BCM2835_PERI_BASE + 0x3000)
	Base Physical Address of the System Timer registers.
#define	BCM2835_GPIO_PADS (BCM2835_PERI_BASE + 0x100000)
	Base Physical Address of the Pads registers.
#define	BCM2835_CLOCK_BASE (BCM2835_PERI_BASE + 0x101000)
	Base Physical Address of the Clock/timer registers.
#define	BCM2835_GPIO_BASE (BCM2835_PERI_BASE + 0x200000)
	Base Physical Address of the GPIO registers.
#define	BCM2835_SPI0_BASE (BCM2835_PERI_BASE + 0x204000)
	Base Physical Address of the SPI0 registers.
#define	BCM2835_BSC0_BASE (BCM2835_PERI_BASE + 0x205000)
	Base Physical Address of the BSC0 registers.
#define	BCM2835_GPIO_PWM (BCM2835_PERI_BASE + 0x20C000)
	Base Physical Address of the PWM registers.
#define	BCM2835_BSC1_BASE (BCM2835_PERI_BASE + 0x804000)
	Base Physical Address of the BSC1 registers.
#define	BCM2835_PAGE_SIZE (4*1024)
	Size of memory page on RPi.
#define	BCM2835_BLOCK_SIZE (4*1024)
	Size of memory block on RPi.
#define	BCM2835_GPFSEL0 0x0000
	GPIO register offsets from BCM2835_GPIO_BASE. Offsets into the GPIO Peripheral block in bytes per 6.1 Register View.
#define	BCM2835_GPFSEL1 0x0004
	GPIO Function Select 1.
#define	BCM2835_GPFSEL2 0x0008
	GPIO Function Select 2.
#define	BCM2835_GPFSEL3 0x000c
	GPIO Function Select 3.
#define	BCM2835_GPFSEL4 0x0010
	GPIO Function Select 4.
#define	BCM2835_GPFSEL5 0x0014
	GPIO Function Select 5.
#define	BCM2835_GPSET0 0x001c
	GPIO Pin Output Set 0.
#define	BCM2835_GPSET1 0x0020
	GPIO Pin Output Set 1.
#define	BCM2835_GPCLR0 0x0028
	GPIO Pin Output Clear 0.
#define	BCM2835_GPCLR1 0x002c
	GPIO Pin Output Clear 1.
#define	BCM2835_GPLEV0 0x0034
	GPIO Pin Level 0.
#define	BCM2835_GPLEV1 0x0038
	GPIO Pin Level 1.
#define	BCM2835_GPEDS0 0x0040
	GPIO Pin Event Detect Status 0.
#define	BCM2835_GPEDS1 0x0044
	GPIO Pin Event Detect Status 1.
#define	BCM2835_GPREN0 0x004c
	GPIO Pin Rising Edge Detect Enable 0.
#define	BCM2835_GPREN1 0x0050
	GPIO Pin Rising Edge Detect Enable 1.
#define	BCM2835_GPFEN0 0x0058
	GPIO Pin Falling Edge Detect Enable 0.
#define	BCM2835_GPFEN1 0x005c
	GPIO Pin Falling Edge Detect Enable 1.
#define	BCM2835_GPHEN0 0x0064
	GPIO Pin High Detect Enable 0.
#define	BCM2835_GPHEN1 0x0068
	GPIO Pin High Detect Enable 1.
#define	BCM2835_GPLEN0 0x0070
	GPIO Pin Low Detect Enable 0.
#define	BCM2835_GPLEN1 0x0074
	GPIO Pin Low Detect Enable 1.
#define	BCM2835_GPAREN0 0x007c
	GPIO Pin Async. Rising Edge Detect 0.
#define	BCM2835_GPAREN1 0x0080
	GPIO Pin Async. Rising Edge Detect 1.
#define	BCM2835_GPAFEN0 0x0088
	GPIO Pin Async. Falling Edge Detect 0.
#define	BCM2835_GPAFEN1 0x008c
	GPIO Pin Async. Falling Edge Detect 1.
#define	BCM2835_GPPUD 0x0094
	GPIO Pin Pull-up/down Enable.
#define	BCM2835_GPPUDCLK0 0x0098
	GPIO Pin Pull-up/down Enable Clock 0.
#define	BCM2835_GPPUDCLK1 0x009c
	GPIO Pin Pull-up/down Enable Clock 1.
#define	BCM2835_PADS_GPIO_0_27 0x002c
	Pad control register offsets from BCM2835_GPIO_PADS.
#define	BCM2835_PADS_GPIO_28_45 0x0030
	Pad control register for pads 28 to 45.
#define	BCM2835_PADS_GPIO_46_53 0x0034
	Pad control register for pads 46 to 53.
#define	BCM2835_PAD_PASSWRD (0x5A << 24)
	Pad Control masks.
#define	BCM2835_PAD_SLEW_RATE_UNLIMITED 0x10
	Slew rate unlimited.
#define	BCM2835_PAD_HYSTERESIS_ENABLED 0x08
	Hysteresis enabled.
#define	BCM2835_PAD_DRIVE_2mA 0x00
	2mA drive current
#define	BCM2835_PAD_DRIVE_4mA 0x01
	4mA drive current
#define	BCM2835_PAD_DRIVE_6mA 0x02
	6mA drive current
#define	BCM2835_PAD_DRIVE_8mA 0x03
	8mA drive current
#define	BCM2835_PAD_DRIVE_10mA 0x04
	10mA drive current
#define	BCM2835_PAD_DRIVE_12mA 0x05
	12mA drive current
#define	BCM2835_PAD_DRIVE_14mA 0x06
	14mA drive current
#define	BCM2835_PAD_DRIVE_16mA 0x07
	16mA drive current
#define	BCM2835_SPI0_CS 0x0000
	SPI Master Control and Status.
#define	BCM2835_SPI0_FIFO 0x0004
	SPI Master TX and RX FIFOs.
#define	BCM2835_SPI0_CLK 0x0008
	SPI Master Clock Divider.
#define	BCM2835_SPI0_DLEN 0x000c
	SPI Master Data Length.
#define	BCM2835_SPI0_LTOH 0x0010
	SPI LOSSI mode TOH.
#define	BCM2835_SPI0_DC 0x0014
	SPI DMA DREQ Controls.
#define	BCM2835_SPI0_CS_LEN_LONG 0x02000000
	Enable Long data word in Lossi mode if DMA_LEN is set.
#define	BCM2835_SPI0_CS_DMA_LEN 0x01000000
	Enable DMA mode in Lossi mode.
#define	BCM2835_SPI0_CS_CSPOL2 0x00800000
	Chip Select 2 Polarity.
#define	BCM2835_SPI0_CS_CSPOL1 0x00400000
	Chip Select 1 Polarity.
#define	BCM2835_SPI0_CS_CSPOL0 0x00200000
	Chip Select 0 Polarity.
#define	BCM2835_SPI0_CS_RXF 0x00100000
	RXF - RX FIFO Full.
#define	BCM2835_SPI0_CS_RXR 0x00080000
	RXR RX FIFO needs Reading ( full)
#define	BCM2835_SPI0_CS_TXD 0x00040000
	TXD TX FIFO can accept Data.
#define	BCM2835_SPI0_CS_RXD 0x00020000
	RXD RX FIFO contains Data.
#define	BCM2835_SPI0_CS_DONE 0x00010000
	Done transfer Done.
#define	BCM2835_SPI0_CS_TE_EN 0x00008000
	Unused.
#define	BCM2835_SPI0_CS_LMONO 0x00004000
	Unused.
#define	BCM2835_SPI0_CS_LEN 0x00002000
	LEN LoSSI enable.
#define	BCM2835_SPI0_CS_REN 0x00001000
	REN Read Enable.
#define	BCM2835_SPI0_CS_ADCS 0x00000800
	ADCS Automatically Deassert Chip Select.
#define	BCM2835_SPI0_CS_INTR 0x00000400
	INTR Interrupt on RXR.
#define	BCM2835_SPI0_CS_INTD 0x00000200
	INTD Interrupt on Done.
#define	BCM2835_SPI0_CS_DMAEN 0x00000100
	DMAEN DMA Enable.
#define	BCM2835_SPI0_CS_TA 0x00000080
	Transfer Active.
#define	BCM2835_SPI0_CS_CSPOL 0x00000040
	Chip Select Polarity.
#define	BCM2835_SPI0_CS_CLEAR 0x00000030
	Clear FIFO Clear RX and TX.
#define	BCM2835_SPI0_CS_CLEAR_RX 0x00000020
	Clear FIFO Clear RX.
#define	BCM2835_SPI0_CS_CLEAR_TX 0x00000010
	Clear FIFO Clear TX.
#define	BCM2835_SPI0_CS_CPOL 0x00000008
	Clock Polarity.
#define	BCM2835_SPI0_CS_CPHA 0x00000004
	Clock Phase.
#define	BCM2835_SPI0_CS_CS 0x00000003
	Chip Select.
#define	BCM2835_BSC_C 0x0000
	BSC Master Control.
#define	BCM2835_BSC_S 0x0004
	BSC Master Status.
#define	BCM2835_BSC_DLEN 0x0008
	BSC Master Data Length.
#define	BCM2835_BSC_A 0x000c
	BSC Master Slave Address.
#define	BCM2835_BSC_FIFO 0x0010
	BSC Master Data FIFO.
#define	BCM2835_BSC_DIV 0x0014
	BSC Master Clock Divider.
#define	BCM2835_BSC_DEL 0x0018
	BSC Master Data Delay.
#define	BCM2835_BSC_CLKT 0x001c
	BSC Master Clock Stretch Timeout.
#define	BCM2835_BSC_C_I2CEN 0x00008000
	I2C Enable, 0 = disabled, 1 = enabled.
#define	BCM2835_BSC_C_INTR 0x00000400
	Interrupt on RX.
#define	BCM2835_BSC_C_INTT 0x00000200
	Interrupt on TX.
#define	BCM2835_BSC_C_INTD 0x00000100
	Interrupt on DONE.
#define	BCM2835_BSC_C_ST 0x00000080
	Start transfer, 1 = Start a new transfer.
#define	BCM2835_BSC_C_CLEAR_1 0x00000020
	Clear FIFO Clear.
#define	BCM2835_BSC_C_CLEAR_2 0x00000010
	Clear FIFO Clear.
#define	BCM2835_BSC_C_READ 0x00000001
	Read transfer.
#define	BCM2835_BSC_S_CLKT 0x00000200
	Clock stretch timeout.
#define	BCM2835_BSC_S_ERR 0x00000100
	ACK error.
#define	BCM2835_BSC_S_RXF 0x00000080
	RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full.
#define	BCM2835_BSC_S_TXE 0x00000040
	TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full.
#define	BCM2835_BSC_S_RXD 0x00000020
	RXD FIFO contains data.
#define	BCM2835_BSC_S_TXD 0x00000010
	TXD FIFO can accept data.
#define	BCM2835_BSC_S_RXR 0x00000008
	RXR FIFO needs reading (full)
#define	BCM2835_BSC_S_TXW 0x00000004
	TXW FIFO needs writing (full)
#define	BCM2835_BSC_S_DONE 0x00000002
	Transfer DONE.
#define	BCM2835_BSC_S_TA 0x00000001
	Transfer Active.
#define	BCM2835_BSC_FIFO_SIZE 16
	BSC FIFO size.
#define	BCM2835_ST_CS 0x0000
	System Timer Control/Status.
#define	BCM2835_ST_CLO 0x0004
	System Timer Counter Lower 32 bits.
#define	BCM2835_ST_CHI 0x0008
	System Timer Counter Upper 32 bits.

Enumerations
enum	bcm2835FunctionSelect { BCM2835_GPIO_FSEL_INPT = 0b000, BCM2835_GPIO_FSEL_OUTP = 0b001, BCM2835_GPIO_FSEL_ALT0 = 0b100, BCM2835_GPIO_FSEL_ALT1 = 0b101, BCM2835_GPIO_FSEL_ALT2 = 0b110, BCM2835_GPIO_FSEL_ALT3 = 0b111, BCM2835_GPIO_FSEL_ALT4 = 0b011, BCM2835_GPIO_FSEL_ALT5 = 0b010, BCM2835_GPIO_FSEL_MASK = 0b111 }
	bcm2835PortFunction Port function select modes for bcm2835_gpio_fsel() More...
enum	bcm2835PUDControl { BCM2835_GPIO_PUD_OFF = 0b00, BCM2835_GPIO_PUD_DOWN = 0b01, BCM2835_GPIO_PUD_UP = 0b10 }
	bcm2835PUDControl Pullup/Pulldown defines for bcm2835_gpio_pud() More...
enum	bcm2835PadGroup { BCM2835_PAD_GROUP_GPIO_0_27 = 0, BCM2835_PAD_GROUP_GPIO_28_45 = 1, BCM2835_PAD_GROUP_GPIO_46_53 = 2 }
	bcm2835PadGroup Pad group specification for bcm2835_gpio_pad() More...
enum	RPiGPIOPin { RPI_GPIO_P1_03 = 0, RPI_GPIO_P1_05 = 1, RPI_GPIO_P1_07 = 4, RPI_GPIO_P1_08 = 14, RPI_GPIO_P1_10 = 15, RPI_GPIO_P1_11 = 17, RPI_GPIO_P1_12 = 18, RPI_GPIO_P1_13 = 21, RPI_GPIO_P1_15 = 22, RPI_GPIO_P1_16 = 23, RPI_GPIO_P1_18 = 24, RPI_GPIO_P1_19 = 10, RPI_GPIO_P1_21 = 9, RPI_GPIO_P1_22 = 25, RPI_GPIO_P1_23 = 11, RPI_GPIO_P1_24 = 8, RPI_GPIO_P1_26 = 7, RPI_V2_GPIO_P1_03 = 2, RPI_V2_GPIO_P1_05 = 3, RPI_V2_GPIO_P1_07 = 4, RPI_V2_GPIO_P1_08 = 14, RPI_V2_GPIO_P1_10 = 15, RPI_V2_GPIO_P1_11 = 17, RPI_V2_GPIO_P1_12 = 18, RPI_V2_GPIO_P1_13 = 27, RPI_V2_GPIO_P1_15 = 22, RPI_V2_GPIO_P1_16 = 23, RPI_V2_GPIO_P1_18 = 24, RPI_V2_GPIO_P1_19 = 10, RPI_V2_GPIO_P1_21 = 9, RPI_V2_GPIO_P1_22 = 25, RPI_V2_GPIO_P1_23 = 11, RPI_V2_GPIO_P1_24 = 8, RPI_V2_GPIO_P1_26 = 7, RPI_V2_GPIO_P5_03 = 28, RPI_V2_GPIO_P5_04 = 29, RPI_V2_GPIO_P5_05 = 30, RPI_V2_GPIO_P5_06 = 31 }
	GPIO Pin Numbers. More...
enum	bcm2835SPIBitOrder { BCM2835_SPI_BIT_ORDER_LSBFIRST = 0, BCM2835_SPI_BIT_ORDER_MSBFIRST = 1 }
	bcm2835SPIBitOrder SPI Bit order Specifies the SPI data bit ordering for bcm2835_spi_setBitOrder() More...
enum	bcm2835SPIMode { BCM2835_SPI_MODE0 = 0, BCM2835_SPI_MODE1 = 1, BCM2835_SPI_MODE2 = 2, BCM2835_SPI_MODE3 = 3 }
	SPI Data mode Specify the SPI data mode to be passed to bcm2835_spi_setDataMode() More...
enum	bcm2835SPIChipSelect { BCM2835_SPI_CS0 = 0, BCM2835_SPI_CS1 = 1, BCM2835_SPI_CS2 = 2, BCM2835_SPI_CS_NONE = 3 }
	bcm2835SPIChipSelect Specify the SPI chip select pin(s) More...
enum	bcm2835SPIClockDivider { BCM2835_SPI_CLOCK_DIVIDER_65536 = 0, BCM2835_SPI_CLOCK_DIVIDER_32768 = 32768, BCM2835_SPI_CLOCK_DIVIDER_16384 = 16384, BCM2835_SPI_CLOCK_DIVIDER_8192 = 8192, BCM2835_SPI_CLOCK_DIVIDER_4096 = 4096, BCM2835_SPI_CLOCK_DIVIDER_2048 = 2048, BCM2835_SPI_CLOCK_DIVIDER_1024 = 1024, BCM2835_SPI_CLOCK_DIVIDER_512 = 512, BCM2835_SPI_CLOCK_DIVIDER_256 = 256, BCM2835_SPI_CLOCK_DIVIDER_128 = 128, BCM2835_SPI_CLOCK_DIVIDER_64 = 64, BCM2835_SPI_CLOCK_DIVIDER_32 = 32, BCM2835_SPI_CLOCK_DIVIDER_16 = 16, BCM2835_SPI_CLOCK_DIVIDER_8 = 8, BCM2835_SPI_CLOCK_DIVIDER_4 = 4, BCM2835_SPI_CLOCK_DIVIDER_2 = 2, BCM2835_SPI_CLOCK_DIVIDER_1 = 1 }
	bcm2835SPIClockDivider Specifies the divider used to generate the SPI clock from the system clock. Figures below give the divider, clock period and clock frequency. Clock divided is based on nominal base clock rate of 250MHz It is reported that (contrary to the documentation) any even divider may used. The frequencies shown for each divider have been confirmed by measurement More...
enum	bcm2835I2CClockDivider { BCM2835_I2C_CLOCK_DIVIDER_2500 = 2500, BCM2835_I2C_CLOCK_DIVIDER_626 = 626, BCM2835_I2C_CLOCK_DIVIDER_150 = 150, BCM2835_I2C_CLOCK_DIVIDER_148 = 148 }
	bcm2835I2CClockDivider Specifies the divider used to generate the I2C clock from the system clock. Clock divided is based on nominal base clock rate of 250MHz More...
enum	bcm2835I2CReasonCodes { BCM2835_I2C_REASON_OK = 0x00, BCM2835_I2C_REASON_ERROR_NACK = 0x01, BCM2835_I2C_REASON_ERROR_CLKT = 0x02, BCM2835_I2C_REASON_ERROR_DATA = 0x04 }
	bcm2835I2CReasonCodes Specifies the reason codes for the bcm2835_i2c_write and bcm2835_i2c_read functions. More...

Variables
volatile uint32_t *	bcm2835_st
volatile uint32_t *	bcm2835_gpio
volatile uint32_t *	bcm2835_pwm
volatile uint32_t *	bcm2835_clk
volatile uint32_t *	bcm2835_pads
volatile uint32_t *	bcm2835_spi0
volatile uint32_t *	bcm2835_bsc0
volatile uint32_t *	bcm2835_bsc1

Detailed Description

The values here are designed to be passed to various functions in the bcm2835 library.

Macro Definition Documentation

#define BCM2835_CORE_CLK_HZ 250000000

Speed of the core clock core_clk.

250 MHz

#define BCM2835_GPFSEL0 0x0000

GPIO register offsets from BCM2835_GPIO_BASE. Offsets into the GPIO Peripheral block in bytes per 6.1 Register View.

GPIO Function Select 0

#define BCM2835_PAD_PASSWRD (0x5A << 24)

Pad Control masks.

Password to enable setting pad mask

#define BCM2835_PADS_GPIO_0_27 0x002c

Pad control register offsets from BCM2835_GPIO_PADS.

Pad control register for pads 0 to 27

Enumeration Type Documentation

enum bcm2835FunctionSelect

bcm2835PortFunction Port function select modes for bcm2835_gpio_fsel()

Enumerator:

BCM2835_GPIO_FSEL_INPT	Input.
BCM2835_GPIO_FSEL_OUTP	Output.
BCM2835_GPIO_FSEL_ALT0	Alternate function 0.
BCM2835_GPIO_FSEL_ALT1	Alternate function 1.
BCM2835_GPIO_FSEL_ALT2	Alternate function 2.
BCM2835_GPIO_FSEL_ALT3	Alternate function 3.
BCM2835_GPIO_FSEL_ALT4	Alternate function 4.
BCM2835_GPIO_FSEL_ALT5	Alternate function 5.
BCM2835_GPIO_FSEL_MASK	Function select bits mask.

enum bcm2835I2CClockDivider

bcm2835I2CClockDivider Specifies the divider used to generate the I2C clock from the system clock. Clock divided is based on nominal base clock rate of 250MHz

Enumerator:

BCM2835_I2C_CLOCK_DIVIDER_2500	2500 = 10us = 100 kHz
BCM2835_I2C_CLOCK_DIVIDER_626	622 = 2.504us = 399.3610 kHz
BCM2835_I2C_CLOCK_DIVIDER_150	150 = 60ns = 1.666 MHz (default at reset)
BCM2835_I2C_CLOCK_DIVIDER_148	148 = 59ns = 1.689 MHz

enum bcm2835I2CReasonCodes

bcm2835I2CReasonCodes Specifies the reason codes for the bcm2835_i2c_write and bcm2835_i2c_read functions.

Enumerator:

BCM2835_I2C_REASON_OK	Success.
BCM2835_I2C_REASON_ERROR_NACK	Received a NACK.
BCM2835_I2C_REASON_ERROR_CLKT	Received Clock Stretch Timeout.
BCM2835_I2C_REASON_ERROR_DATA	Not all data is sent / received.

enum bcm2835PadGroup

bcm2835PadGroup Pad group specification for bcm2835_gpio_pad()

Enumerator:

BCM2835_PAD_GROUP_GPIO_0_27	Pad group for GPIO pads 0 to 27.
BCM2835_PAD_GROUP_GPIO_28_45	Pad group for GPIO pads 28 to 45.
BCM2835_PAD_GROUP_GPIO_46_53	Pad group for GPIO pads 46 to 53.

enum bcm2835PUDControl

bcm2835PUDControl Pullup/Pulldown defines for bcm2835_gpio_pud()

Enumerator:

BCM2835_GPIO_PUD_OFF	Off ? disable pull-up/down.
BCM2835_GPIO_PUD_DOWN	Enable Pull Down control.
BCM2835_GPIO_PUD_UP	Enable Pull Up control.

enum bcm2835SPIBitOrder

bcm2835SPIBitOrder SPI Bit order Specifies the SPI data bit ordering for bcm2835_spi_setBitOrder()

Enumerator:

BCM2835_SPI_BIT_ORDER_LSBFIRST	LSB First.
BCM2835_SPI_BIT_ORDER_MSBFIRST	MSB First.

enum bcm2835SPIChipSelect

bcm2835SPIChipSelect Specify the SPI chip select pin(s)

Enumerator:

BCM2835_SPI_CS0	Chip Select 0.
BCM2835_SPI_CS1	Chip Select 1.
BCM2835_SPI_CS2	Chip Select 2 (ie pins CS1 and CS2 are asserted)
BCM2835_SPI_CS_NONE	No CS, control it yourself.

enum bcm2835SPIClockDivider

bcm2835SPIClockDivider Specifies the divider used to generate the SPI clock from the system clock. Figures below give the divider, clock period and clock frequency. Clock divided is based on nominal base clock rate of 250MHz It is reported that (contrary to the documentation) any even divider may used. The frequencies shown for each divider have been confirmed by measurement

Enumerator:

BCM2835_SPI_CLOCK_DIVIDER_65536	65536 = 262.144us = 3.814697260kHz
BCM2835_SPI_CLOCK_DIVIDER_32768	32768 = 131.072us = 7.629394531kHz
BCM2835_SPI_CLOCK_DIVIDER_16384	16384 = 65.536us = 15.25878906kHz
BCM2835_SPI_CLOCK_DIVIDER_8192	8192 = 32.768us = 30/51757813kHz
BCM2835_SPI_CLOCK_DIVIDER_4096	4096 = 16.384us = 61.03515625kHz
BCM2835_SPI_CLOCK_DIVIDER_2048	2048 = 8.192us = 122.0703125kHz
BCM2835_SPI_CLOCK_DIVIDER_1024	1024 = 4.096us = 244.140625kHz
BCM2835_SPI_CLOCK_DIVIDER_512	512 = 2.048us = 488.28125kHz
BCM2835_SPI_CLOCK_DIVIDER_256	256 = 1.024us = 976.5625MHz
BCM2835_SPI_CLOCK_DIVIDER_128	128 = 512ns = = 1.953125MHz
BCM2835_SPI_CLOCK_DIVIDER_64	64 = 256ns = 3.90625MHz
BCM2835_SPI_CLOCK_DIVIDER_32	32 = 128ns = 7.8125MHz
BCM2835_SPI_CLOCK_DIVIDER_16	16 = 64ns = 15.625MHz
BCM2835_SPI_CLOCK_DIVIDER_8	8 = 32ns = 31.25MHz
BCM2835_SPI_CLOCK_DIVIDER_4	4 = 16ns = 62.5MHz
BCM2835_SPI_CLOCK_DIVIDER_2	2 = 8ns = 125MHz, fastest you can get
BCM2835_SPI_CLOCK_DIVIDER_1	0 = 262.144us = 3.814697260kHz, same as 0/65536

enum bcm2835SPIMode

SPI Data mode Specify the SPI data mode to be passed to bcm2835_spi_setDataMode()

Enumerator:

BCM2835_SPI_MODE0	CPOL = 0, CPHA = 0.
BCM2835_SPI_MODE1	CPOL = 0, CPHA = 1.
BCM2835_SPI_MODE2	CPOL = 1, CPHA = 0.
BCM2835_SPI_MODE3	CPOL = 1, CPHA = 1.

enum RPiGPIOPin

GPIO Pin Numbers.

Here we define Raspberry Pin GPIO pins on P1 in terms of the underlying BCM GPIO pin numbers. These can be passed as a pin number to any function requiring a pin. Not all pins on the RPi 26 bin IDE plug are connected to GPIO pins and some can adopt an alternate function. RPi version 2 has some slightly different pinouts, and these are values RPI_V2_*. At bootup, pins 8 and 10 are set to UART0_TXD, UART0_RXD (ie the alt0 function) respectively When SPI0 is in use (ie after bcm2835_spi_begin()), pins 19, 21, 23, 24, 26 are dedicated to SPI and cant be controlled independently

Enumerator:

RPI_GPIO_P1_03	Version 1, Pin P1-03.
RPI_GPIO_P1_05	Version 1, Pin P1-05.
RPI_GPIO_P1_07	Version 1, Pin P1-07.
RPI_GPIO_P1_08	Version 1, Pin P1-08, defaults to alt function 0 UART0_TXD.
RPI_GPIO_P1_10	Version 1, Pin P1-10, defaults to alt function 0 UART0_RXD.
RPI_GPIO_P1_11	Version 1, Pin P1-11.
RPI_GPIO_P1_12	Version 1, Pin P1-12.
RPI_GPIO_P1_13	Version 1, Pin P1-13.
RPI_GPIO_P1_15	Version 1, Pin P1-15.
RPI_GPIO_P1_16	Version 1, Pin P1-16.
RPI_GPIO_P1_18	Version 1, Pin P1-18.
RPI_GPIO_P1_19	Version 1, Pin P1-19, MOSI when SPI0 in use.
RPI_GPIO_P1_21	Version 1, Pin P1-21, MISO when SPI0 in use.
RPI_GPIO_P1_22	Version 1, Pin P1-22.
RPI_GPIO_P1_23	Version 1, Pin P1-23, CLK when SPI0 in use.
RPI_GPIO_P1_24	Version 1, Pin P1-24, CE0 when SPI0 in use.
RPI_GPIO_P1_26	Version 1, Pin P1-26, CE1 when SPI0 in use.
RPI_V2_GPIO_P1_03	Version 2, Pin P1-03.
RPI_V2_GPIO_P1_05	Version 2, Pin P1-05.
RPI_V2_GPIO_P1_07	Version 2, Pin P1-07.
RPI_V2_GPIO_P1_08	Version 2, Pin P1-08, defaults to alt function 0 UART0_TXD.
RPI_V2_GPIO_P1_10	Version 2, Pin P1-10, defaults to alt function 0 UART0_RXD.
RPI_V2_GPIO_P1_11	Version 2, Pin P1-11.
RPI_V2_GPIO_P1_12	Version 2, Pin P1-12.
RPI_V2_GPIO_P1_13	Version 2, Pin P1-13.
RPI_V2_GPIO_P1_15	Version 2, Pin P1-15.
RPI_V2_GPIO_P1_16	Version 2, Pin P1-16.
RPI_V2_GPIO_P1_18	Version 2, Pin P1-18.
RPI_V2_GPIO_P1_19	Version 2, Pin P1-19, MOSI when SPI0 in use.
RPI_V2_GPIO_P1_21	Version 2, Pin P1-21, MISO when SPI0 in use.
RPI_V2_GPIO_P1_22	Version 2, Pin P1-22.
RPI_V2_GPIO_P1_23	Version 2, Pin P1-23, CLK when SPI0 in use.
RPI_V2_GPIO_P1_24	Version 2, Pin P1-24, CE0 when SPI0 in use.
RPI_V2_GPIO_P1_26	Version 2, Pin P1-26, CE1 when SPI0 in use.
RPI_V2_GPIO_P5_03	Version 2, Pin P5-03.
RPI_V2_GPIO_P5_04	Version 2, Pin P5-04.
RPI_V2_GPIO_P5_05	Version 2, Pin P5-05.
RPI_V2_GPIO_P5_06	Version 2, Pin P5-06.

Variable Documentation

volatile uint32_t* bcm2835_bsc0

Base of the BSC0 registers. Available after bcm2835_init has been called

volatile uint32_t* bcm2835_bsc1

Base of the BSC1 registers. Available after bcm2835_init has been called

volatile uint32_t* bcm2835_clk

Base of the CLK registers. Available after bcm2835_init has been called

volatile uint32_t* bcm2835_gpio

Base of the GPIO registers. Available after bcm2835_init has been called

volatile uint32_t* bcm2835_pads

Base of the PADS registers. Available after bcm2835_init has been called

volatile uint32_t* bcm2835_pwm

Base of the PWM registers. Available after bcm2835_init has been called

volatile uint32_t* bcm2835_spi0

Base of the SPI0 registers. Available after bcm2835_init has been called

volatile uint32_t* bcm2835_st

Base of the ST (System Timer) registers. Available after bcm2835_init has been called

Macros

Enumerations

Variables

Detailed Description

Macro Definition Documentation

Enumeration Type Documentation

Variable Documentation